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1/13 august 2004 high speed: f max = 145mhz (typ.) at v cc = 3.3v 5v tolerant inputs input voltage level: v il =0.8v, v ih =2v at v cc =3v low power dissipation: i cc = 2 a (max.) at t a =25c low noise: v olp = 0.3v (typ.) at v cc = 3.3v symmetrical output impedance: |i oh | = i ol = 4ma (min) balanced propagation delays: t plh ? t phl operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) pin and function compatible with 74 series 74 improved latch-up immunity power down protection on inputs description the 74lvx74 is a low voltage cmos dual d-type flip-flop with preset and clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power, battery operated and low noise 3.3v applications. a signal on the d input is transferred to the q output during the positive going transition of the clock pulse. clr and pr are independent of the clock and accomplished by a low setting on the appropriate input. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v system. it combines high speed performance with the true cmos low power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvx74 low voltage cmos dual d-type flip flop with preset and clear (5v tolerant inputs) figure 1: pin connection and iec logic symbols table 1: order codes package t & r sop 74lvx74mtr tssop 74LVX74TTR tssop sop rev. 3
74lvx74 2/13 figure 2: input equivalent circuit table 2: pin description table 3: truth table x : don?t care figure 3: logic diagram this logic diagram has not be used to estimate propagation delays pin n symbol name and function 1, 13 1clr , 2clr asynchronous reset - direct input 2, 12 1d, 2d data inputs 3, 11 1ck, 2ck clock input (low to high, edge triggered) 4, 10 1pr , 2pr asynchronous set - direct input 5, 9 1q, 2q true flip-flop outputs 6, 8 1q , 2q complement flip-flop outputs 7 gnd ground (0v) 14 v cc positive supply voltage inputs outputs function clr pr dckq q lhxxlh clear h l x x h l preset llxxhh hhl lh hhh hl hhx q n q n no change
74lvx74 3/13 table 4: absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. table 5: recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2.0v table 6: dc specifications symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) (v cc = 3.3v) 0 to 100 ns/v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 2.0 2.0 2.0 3.6 2.4 2.4 2.4 v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 0.8 0.8 0.8 3.6 0.8 0.8 0.8 v oh high level output voltage 2.0 i o =-50 a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 a 2.9 3.0 2.9 2.9 3.0 i o =-4 ma 2.58 2.48 2.4 v ol low level output voltage 2.0 i o =50 a 0.0 0.1 0.1 0.1 v 3.0 i o =50 a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 i i input leakage current 3.6 v i = 5v or gnd 0.1 1 1 a i cc quiescent supply current 3.6 v i = v cc or gnd 22020 a
74lvx74 4/13 table 7: dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. table 8: ac electrical characteristics (input t r = t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l = 50 pf 0.3 0.5 v v olv -0.5 -0.3 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v ild dynamic low voltage input (note 1, 3) 3.3 0.8 symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time ck to q or q 2.7 15 7.3 15.0 1.0 18.5 1.0 18.5 ns 2.7 50 9.8 18.5 1.0 22.0 1.0 22.0 3.3 (*) 15 5.7 9.7 1.0 11.5 1.0 11.5 3.3 (*) 50 8.2 13.2 1.0 15.0 1.0 15.0 t plh t phl propagation delay time pr or clr to q or q 2.7 15 8.4 15.6 1.0 18.5 1.0 18.5 ns 2.7 50 10.9 19.1 1.0 22.0 1.0 22.0 3.3 (*) 15 6.6 10.1 1.0 12.0 1.0 12.0 3.3 (*) 50 9.1 13.6 1.0 15.5 1.0 15.5 t w minimum pulse width high or low, ck 2.7 50 8.5 10.0 10.0 ns 3.3 (*) 50 6.0 7.0 7.0 t w(l) minimum pulse width low pr or clr 2.7 50 8.5 10.0 10.0 ns 3.3 (*) 50 6.0 7.0 7.0 t s minimum setup time d to ck high or low 2.7 50 8.0 9.5 9.5 ns 3.3 (*) 50 5.5 6.5 6.5 t h minimum hold time d to ck high or low 2.7 50 0.5 0.5 0.5 ns 3.3 (*) 50 0.5 0.5 0.5 t rem minimum removal time pr or clr to ck 2.7 50 6.5 7.5 7.5 ns 3.3 (*) 50 5.0 5.0 5.0 f max maximum clock frequency 2.7 15 55 135 50 50 mhz 2.750 45604040 3.3 (*) 15 95 145 80 80 3.3 (*) 50 60 85 50 50 t oslh t oshl output to output skew time (note1, 2) 2.7 50 0.5 1.0 1.5 1.5 ns 3.3 (*) 50 0.5 1.0 1.5 1.5
74lvx74 5/13 table 9: capacitive characteristics 1) c pd is defined as the value of the ic?s internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /2 (per circuit) figure 4: test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 ? ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 3.3 4 10 10 10 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10 mhz 25 pf
74lvx74 6/13 figure 5: waveform - propagation delays, setup and hold times (f=1mhz; 50% duty cycle) figure 6: waveform - recovery time (f=1mhz; 50% duty cycle)
74lvx74 7/13 figure 7: waveform - propagation delays, minimum pulse width (f=1mhz; 50% duty cycle) figure 8: waveform - minimum pulse width
74lvx74 8/13 dim. mm. inch min. typ max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.1 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 8.55 8.75 0.337 0.344 e 3.8 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.2 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.4 1.27 0.016 0.050 k0 8 0 8 ddd 0.100 0.004 so-14 mechanical data 0016019d
74lvx74 9/13 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0? 8?0? 8? l 0.45 0.60 0.75 0.018 0.024 0.030 tssop14 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080337d
74lvx74 10/13 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.4 6.6 0.252 0.260 bo 9 9.2 0.354 0.362 ko 2.1 2.3 0.082 0.090 po 3.9 4.1 0.153 0.161 p 7.9 8.1 0.311 0.319 tape & reel so-14 mechanical data
74lvx74 11/13 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.7 6.9 0.264 0.272 bo 5.3 5.5 0.209 0.217 ko 1.6 1.8 0.063 0.071 po 3.9 4.1 0.153 0.161 p 7.9 8.1 0.311 0.319 tape & reel tssop14 mechanical data
74lvx74 12/13 table 10: revision history date revision description of changes 27-aug-2004 3 ordering codes revision - pag. 1.
74lvx74 13/13 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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